There has been known a semiconductor integrated circuit in which a main block and a peripheral block including a logic circuit are mounted, in a mixed manner, on a semiconductor substrate (refer to Patent Document 1). A main circuit is formed in the main block on the semiconductor substrate, and includes a first trench capacitor. An analog circuit is formed in the peripheral block on the semiconductor substrate, and includes a second trench capacitor. The analog circuit includes at least either a phase locked loop (PLL) or a regulator.
Patent Document 1: Japanese Laid-open Patent Publication No. 2013-110254
An IP (Intellectual Property) core is a circuit of electronic component of functional unit for configuring a semiconductor integrated circuit. The semiconductor integrated circuit is configured by combining various IP cores. The IP core is demanded to achieve not only high performance (speed-up, low power consumption, low noise) but also reduction in size. However, when an inside of the IP core is optimized, a dead space (free space) is sometimes generated in the IP core.